When an electronic circuit is implemented using complementary metal-oxide semiconductor (CMOS) technology, there is a trade-off between performance and power. This trade-off is related to the threshold voltages of the transistors used to form the circuit. The threshold voltage of a typical n-channel transistor is a positive value; the threshold voltage of a typical p-channel transistor is a negative value. Someone of ordinary skill in the art, however, will recognize that in some cases, the threshold voltage of a n-channel transistor can be a negative value and the threshold voltage of a p-channel transistor can be a positive value. Nominally, the threshold voltage of a transistor is the minimum voltage that must be applied to the gate of the transistor in order for the transistor to conduct or "turn on;" otherwise, the transistor is "turned off." However, more specifically, a subthreshold current, which decreases exponentially with gate to source voltage, may still flow through the transistor for a gate voltage below the threshold voltage. A relatively low threshold voltage allows a relatively large amount of drive current to flow through the transistor. A larger drive current allows a faster transition of the transistor's output voltage between high and low. Rapid transition correlates to high performance for the circuit. However, a low threshold voltage also allows a larger amount of leakage current to flow through the transistor when the gate to source voltage is near zero. Leakage current is undesirable because it causes the circuit to unnecessarily consume power. Alternatively, if the transistor has a high threshold voltage, only a small amount of leakage current can flow through the transistor, but drive current will also be limited. This trade-off in power and performance in selection of a threshold voltage becomes more pronounced as supply voltage values are lowered.
The threshold voltage of a fully depleted transistor can be made lower or higher by applying different bias voltages to the substrate on which the transistor is formed, thereby affecting the amount of leakage current which can flow through the transistor. For a typical n-channel transistor, a more positive voltage bias applied at the substrate lowers the threshold voltage of the transistor (usually in the sense that the absolute magnitude of the threshold voltage is reduced, but also in the sense of transitioning through zero to a negative value), thereby allowing more drive current to flow through the transistor but also increasing the subthreshold leakage current. A more negative voltage bias applied at the substrate raises the threshold voltage of a typical n-channel transistor (usually in the sense that the absolute magnitude of the threshold voltage is increased, but also in the sense of transitioning through zero to a positive value), thereby reducing the amount of leakage current that flows through the transistor while also lowering the drive current. For a typical p-channel transistor, a more positive voltage bias applied at the substrate raises the threshold voltage (usually in the sense that the absolute magnitude of the threshold voltage is increased) and a more negative voltage bias lowers its threshold voltage (usually in the sense that the absolute magnitude of the threshold voltage is decreased).
Typically, the performance of, and leakage current in, a prior CMOS circuit depended on both the n-channel and p-channel transistors from which the circuit was formed. These prior circuits were designed so that the threshold voltages of the n-channel and p-channel transistors were sufficient to prevent leakage current above a predetermined level, while also allowing a maximum amount of drive current to flow through the transistors. To prevent leakage current from exceeding the predetermined level, the threshold voltage of the n-channel transistors was generally a positive value and the threshold voltage of the p-channel transistors was generally a negative value, with the two threshold voltages substantially equal in magnitude. The circuit was then designed to operate with the threshold voltages of the transistors within an expected range of the nominal values.
Although it has been recognized that the threshold voltage of fully depleted silicon-on-insulator (SOI) transistors can be adjusted by substrate bias (as discussed above), such bias was not used to improve the trade-off between performance and power in prior CMOS circuits. More specifically, if n-channel and p-channel fully-depleted transistors were formed on the same substrate, a change to the common substrate bias would produce opposite effects in the power/performance trade-offs of the n-channel and the p-channel transistors. For example, if a 10.0 V voltage bias was applied to the substrate to lower the threshold voltage of the n-channel transistors, the threshold voltage of the p-channel transistors was raised. Thus, although more drive current could flow through the n-channel transistors, less drive current could flow through the p-channel transistors. Accordingly, the drive current in the prior CMOS circuit would not be substantially increased. In a similar manner, if a -10.0 V voltage bias was applied to the substrate to raise the threshold voltage of the n-channel transistors, the threshold voltage of the p-channel transistors would be lowered. Consequently, although leakage current flowing through the n-channel transistors was reduced, leakage current in the p-channel transistors would be increased. Thus, the overall leakage current in the CMOS circuit was not substantially reduced. Consequently, in prior CMOS circuits, the use of common substrate voltage was not previously considered effective to adjust threshold voltages between different modes of operation.
Accordingly, a need has arisen for a method for substantially reducing the trade-off between performance and power in a CMOS circuit.